1. Field of the Invention
The present invention relates generally to integrated circuit packaging, and more specifically to a memory stack with an integrated interconnect and mounting structure.
2. Related Art
As system designers sought to achieve higher densities in circuit layout, they pioneered the development of three-dimensional memory structures. Such three-dimensional memory structures are commonly known as memory stacks. Memory stacks encompass/span/require less circuit-board surface area because the memory chips are stacked vertically as opposed to laid out horizontally. Thus, while board height may be increased due to circuit stacking, board area is conserved.
Several conventional memory stacks are currently in use. These conventional stacks can best be described through the methods by which they are made. The first memory stack uses specially modified DRAM (Dynamic Random Access Memory) dice manufactured according to the method now described. According to this method, the dice are first exposed to a post process passivation and metalization step to form interconnection leads to the dice edge. The dice are then thinned, to increase density and provide a highly planar dice interface. The dice are then tested and stacked to form a cube. The cube edges are lapped and processed to expose the dice interconnections. Finally, interconnection bonding leads and pads are formed.
According to a second method of producing a memory stack, the RAM dice are wire-bonded to a substrate that is typically a tape form of substrate. The dice are separated, stacked, and bonded to form a cube. After bonding, the cube is cut with a diamond saw to expose the bond wire ends. These cubes are then plated and a laser used to form lands between I/O (Input/Output) and interconnect leads. According to this method, the die/substrate tape may be electrically tested to isolate problem dice prior to stacking and bonding.
A third method of fabrication utilizes conventional DRAM die bonded into a carrier, and wire bonded to I/O pads on the carrier. These loaded carriers are then electrically tested and burned in. After burn-in, the carriers are filled with thermal epoxy and tested again. These filled carriers are then stacked and interfaces are formed on the faces thereof.
Presently, there are no methods for providing burned-in and tested dice when the dice are purchased in water form. As a result, according to the first and second production methods described above, there can be a certain amount of device fall-out due to faults occurring on the wafer. Additionally, there is typically a significant amount tall-out due to the numerous process steps required with these two methods. Furthermore, this great number of process steps tends to increase tile total package cost.
A further drawback of the first two methods is that, because there is no method for assuring that the dice placed onto the stack will survive the subsequent processing, redundant devices must be added into the stack.
The third method for manufacturing memory stacks described above also has disadvantages. One disadvantage is that known good dice are typically priced higher than conventionally-packaged DRAM parts. Additionally, the processing steps, the carriers, and the testing steps raise the cost of these memory stacks.